Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. FIG. 1 is a simplified illustration of one type of PLD, the Field Programmable Gate Array (FPGA). An FPGA typically includes an array of configurable logic blocks (LBs 101a-101i) and programmable input/output blocks (I/Os 102a-102d). The LBs and I/O blocks are interconnected by a programmable interconnect structure that includes a large number of interconnect lines 103 interconnected by programmable interconnect points (PIPs 104, shown as small circles in FIG. 1). PIPs are often coupled into groups (e.g., group 105) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. Some FPGAs also include additional logic blocks with special purposes (not shown), e.g., delay lock loops (DLLs), random access memory (RAM), and so forth.
The interconnect structure and logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the interconnection array and logic blocks are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA. In FPGAs, for example, configuration memory cells are typically implemented as static RAM cells. Each FPGA typically contains many thousands or even millions of these static RAM configuration memory cells.
When bombarded by high-energy particles, a static RAM cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. These inadvertent and undesired state changes are known as “single event upsets”, or SEUs. Sometimes an SEU has no effect on the functionality of the design, e.g., when the SEU shorts together two unused interconnect lines. At other times, an SEU can change the function of an FPGA such that the circuit implemented in the FPGA no longer functions properly.
The smaller geometries, lower operating voltages, and larger numbers of memory cells included in new generations of PLDs can render these devices more susceptible to SEUs than their predecessors. Therefore, it is desirable to provide methods of reducing the susceptibility to SEUs of a design implemented in a PLD. It is further desirable to reduce the susceptibility to SEUs of any integrated circuit that includes static memory cells.